this document describes valueram s 512m x 64-bit (4gb) ddr3l-1600 cl11 sdram (synchronous dram), 1rx8, low voltage, memory module, based on eight 512m x 8-bit fbga components. the spd is programmed to jedec standard latency ddr3-1600 timing of 11-11-11 at 1.35v or 1.5v. this 204-pin sodimm uses gold contact fingers. the electrical and mechanical specifications are as follows::


features:



jedec standard 1.35v (1.28v ~ 1.45v) and 1.5v (1.425v ~ 1.575v) power supply

vddq = 1.35v (1.28v ~ 1.45v) and 1.5v (1.425v ~ 1.575v)

800mhz fck for 1600mb/sec/pin

8 independent internal bank

programmable cas latency: 11, 10, 9, 8, 7, 6

programmable additive latency: 0, cl - 2, or cl - 1 clock

8-bit pre-fetch

burst length: 8 (interleave without any limit, sequential with starting address 000 only), 4 with tccd = 4 which does not allow seamless read or write [either on the fly using a12 or mrs]

bi-directional differential data strobe

internal (self) calibration : internal self calibration through zq pin (rzq : 240 ohm 1%)

on die termination using odt pin

average refresh period 7.8us at lower than tcase 85 c, 3.9us at 85 c < tcase < 95 c

asynchronous reset

pcb: height 1.18 (30mm), double sided component

cl (idd)
11 cycles